2018

  • Improving the Error Behavior of DRAM by Exploiting its Z-Channel Property
    K. Kraft, M. Jung, C. Sudarshan, D. M. Mathew, C. Weis, N. Wehn. Accepted for Publication, IEEE Conference Design, Automation and Test in Europe (DATE), March, 2018, Dresden, Germany

  • An Analysis on Retention Error Behavior and Power Consumption of Recent DDR4 DRAMs
    D, M. Mathew, M. Schultheis, C. C. Rheinländer, C. Sudarshan, M. Jung, C. Weis, N. Wehn. Accepted for Publication, IEEE Conference Design, Automation and Test in Europe (DATE), March, 2018, Dresden, Germany

2017

  • A Memory Centric Architecture of the Link Assessment Algorithm in Large Graphs (DOI)
    C. Brugger, V. Grigorovici, M. Jung, C. De Schryver, C. Weis, N. Wehn, K. Zweig.IEEE Design & Test, 2017

  • Integrating DRAM Power-Down Modes in gem5 and Quantifying their Impact (DOI, ACM Free Access)
    R. Jagtap, M. Jung, W. Elsasser, C. Weis, A. Hansson, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2017), October, 2017, Washington, DC, USA

  • Using Run-Time Reverse-Engineering to Optimize DRAM Refresh (DOI, ACM Free Access)
    D. M. Mathew, É. F. Zulian, M. Jung, K. Kraft, C. Weis, B. Jacob, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2017), October, 2017, Washington, DC, USA

  • A New State Model for DRAMs Using Petri Nets (Link)
    M. Jung, K. Kraft, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2017, Samos Island, Greece.

  • Supervised Testing of Concurrent Software in Embedded Systems (Link)
    J. Jahic, M. Jung, T. Kuhn, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2017, Samos Island, Greece.

  • System Simulation with gem5 and SystemC: The Keystone for Full Interoperability (Link)
    C. Menard, M. Jung, J. Castrillon, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2017, Samos Island, Greece.

  • Support Development and Testing of Concurrent Software through Supervised Software Execution (Link)
    J. Jahic, T. Kuhn, M. Jung, N. Wehn. Advanced Computer Architecture and Compilation for High-Performance Embedded Systems (ACACES), July, 2017, Fiuggi, Italy.

  • A Platform to Analyze DDR3 DRAM’s Power and Retention Time (DOI)
    M. Jung, D. Mathew, C. Rheinländer, C. Weis, N. Wehn. IEEE Design & Test, 2017.

  • 3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems (DOI)
    P. Liu, A. Hemani, K. Paul, C. Weis, M. Jung, N. Wehn. International Journal of Parallel Programming (IJPP), Springer, April 2017.

  • System-Level Modeling, Analysis and Optimization of DRAM Memories and Controller Architectures (Amazon)
    M. Jung. Forschungsberichte Mikroelektronik (26), University of Kaiserslautern, May 2017.

  • A Bank-Wise DRAM Power Model for System Simulations (DOI, ACM Free Access)
    D. M. Mathew, É. F. Zulian, S. Kannoth, M. Jung, C. Weis, N. Wehn. International Conference on High-Performance and Embedded Architectures and Compilers 2016 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), Stockholm, 2017.

2016

  • A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D–Stacked Architecture (DOI)
    P. Liu, A. Hemani1, K. Paul, C. Weis, M. Jung, N. Wehn. International Journal of Signal Processing Systems, Springer, 2016.

  • DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool (DOI)
    C. Weis, A. Mutaal, O. Naji, M. Jung, A. Hansson, N. Wehn. International Journal of Parallel Programming (IJPP), Springer, 2016.

  • 3D Memories
    C. Weis, M. Jung, N. Wehn. Accepted for publication, Book chapter in the Handbook of 3D Integration Vol 4, Wiley-VCH, 2016.

  • A New Bank Sensitive DRAMPower Model for Efficient Design Space Exploration (DOI)
    M. Jung, D. M. Mathew, É. F. Zulian, C. Weis, N. Wehn. International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2016), September, 2016, Bremen, Germany

  • An Application Specific DRAM Memory Controller Generator (DOI, ACM Free Access)
    M. Jung, I. Heinrich, M. Natale, D. M. Mathew, C. Weis, S. Krumke, N. Wehn. International Symposium on Memory Systems (MEMSYS 2016), October, 2016, Washington, DC, USA.
    Most Creative Presentation Award.

  • Reverse Engineering of DRAMs: Row Hammer with Crosshair (DOI, ACM Free Access)
    M. Jung, C. Rheinländer, C. Weis, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2016), October, 2016, Washington, DC, USA.
    Chair's Choice Best Paper Award.

  • Exploring System Performance using Elastic Traces: Fast, Accurate and Portable
    R. Jagtap, S. Diestelhorst, A. Hansson, M. Jung and N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece

  • Approximate Computing with Partially Unreliable Dynamic Random Access Memory: Approximate DRAM (DOI, ACM Free Access)
    M. Jung, D. Mathew, C. Weis, N. Wehn. In Proc. IEEE/ACM Design Automation Conference (DAC), June, 2016, Austin, TX, USA.

  • Efficient Reliability Management in SoCs - An Approximate DRAM Perspective (DOI)
    M. Jung, D. Mathew, C. Weis, N. Wehn. 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Special Session: Cross-Layer Resilience: Snapshots from the Frontier of Design, January, 2016, Macao, China.

2015

  • A Cross Layer Approach for Efficient Thermal Management in 3D Stacked SoCs (DOI)
    M. Jung, C. Weis, N. Wehn. Journal of Microelectronics Reliability, Elsevier 2015.

  • Reliability and Thermal Challenges in 3D Integrated Embedded Systems (PDF)
    C. Weis, M. Jung, N. Wehn. 1st International ESWEEK Workshop on Resiliency in Embedded Electronic Systems, October, 2015, Amsterdam, The Netherlands.

  • Omitting Refresh - A Case Study for Commodity and Wide I/O DRAMs (DOI, ACM Free Access)
    M. Jung, Éder Zulian, M. Mathew, M. Herrmann, C. Brugger, C. Weis, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2015), October, 2015, Washington, DC, USA.

  • DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework (DOI)
    M. Jung, C. Weis, N. Wehn. IPSJ Transactions on System LSI Design Methodology (T-SLDM), October, 2015.

  • A High-Level DRAM Timing, Power and Area Exploration Tool (DOI)
    O. Naji, A. Hansson, C. Weis, M. Jung, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2015, Samos Island, Greece

  • Thermal Aspects and High-level Explorations of 3D stacked DRAMs (DOI)
    C. Weis, M. Jung, C. Santos, P. Vivet, O. Naji, A. Hansson, N. Wehn. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July, 2015, Montpellier, France.

  • A Custom Computing System for Finding Similarties in Complex Networks (DOI)
    C. Brugger, V. Grigorovici, M. Jung, C. Weis, C. De Schryver, K. Zweig, N. Wehn. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July, 2015, Montpellier, France.
    Amar Mukherjee Best Paper Award

  • Coupling gem5 with SystemC TLM 2.0 Virtual Platforms (PPTX)
    M. Jung, N. Wehn. gem5 User Workshop, International Symposium on Computer Architecture (ISCA), June, 2015, Portland, OR, USA.

  • Virtual Development on Mixed Abstraction Levels: an Agricultural Vehicle Case Study (PDF)
    M. Jung, T. Purusothaman, X. Pan, S. Piao, T. Kuhn, C. Grimm, K. Berns, N. Wehn., Synopsys Users Group Conference (SNUG), June, 2015, Munich, Germany.

  • Retention Time Measurements and Modelling of Bit Error Rates of WIDE-I/O DRAM in MPSoCs (PDF)
    C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn., IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France.

2014

  • Thermal and Power Aspects of MPSoCs with WIDE I/O DRAMs (Link)
    Invited Talk, D43D: The 6th Workshop on Design for 3D Silicon Integration, June 23-24, 2014, Lausanne, Switzerland

  • Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs (DOI)
    M. Jung, M. Sadri, C. Weis, N. Wehn, L. Benini., VLSI-SoC, October, 2014, Playa del Carmen, Mexico.

  • Thermal Modelling of 3D Stacked DRAM with Virtual Platforms (PDF)
    M. Jung, M. Sadri, N. Wehn. Ninth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES14), July, 2014, Fiuggi, Italy.

  • Energy Optimization in 3D MPSoCs with Wide-I/O DRAM (DOI)
    M. Sadri, M. Jung, C. Weis, N. Wehn, L. Benini.Conference Design, Automation and Test in Europe (DATE), March, 2014, Dresden, Germany.

2013

  • Virtual Platforms for Fast Exploration of Computing Systems in Finance (PDF)
    C. Brugger, M. Jung, S. Omland. Young Researcher Symposium 2013, November, 2013, Kaiserslautern.
    1. Best Paper Award.

  • Virtual Platforms for Fast Memory Subsystem Exploration Using gem5 and TLM2.0 (PDF)
    M. Jung, M. Sadri, N. Wehn. Ninth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES13), July, 2013, Fiuggi, Italy.

  • Virtual Platforms for Memory Controller Design Space Exploration
    M. Jung, Designers Track Talk. IEEE/ACM Design Automation Conference (DAC), June, 2013, Austin, TX, USA.

  • TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems
    M. Jung, Work-in-Progress Poster Session, IEEE/ACM Design Automation Conference (DAC), June, 2013, Austin, TX, USA.

  • Power Modelling of 3D-Stacked Memories with TLM2.0 based Virtual Platforms (PDF)
    M. Jung, C. Weis, P. Bertram, N. Wehn.Synopsys User Group Conference (SNUG), May, 2013, Munich, Germany.

  • TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration (DOI, ACM Free Access)
    M. Jung, C. Weis, N. Wehn, K. Chandrasekar.
    International Conference on High-Performance and Embedded Architectures and Compilers
    2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO),
    January, 2013, Berlin.

2012

  • A Scalable Multi-Core ASIP Virtual Platform For Standard-Compliant Trellis Decoding (PDF)
    M. Jung, C. Brehm, N. Wehn.
    Synopsys User Group Conference (SNUG), May, 2012, Munich, Germany. 

  • Energy Efficient Acceleration and Evaluation of Financial Computations Towards Real-Time Pricing (Link)
    C. de Schryver, M. Jung, N. Wehn, H. Marxen, A. Kostiuk, R. Korn. 
    Proceedings of the 15th International Conference on Knowledge-Based and Intelligent Information & Engineering Systems (KES), pages 177-186, September, 2011, Kaiserslautern. 
 

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